(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of increasing SiN corner selectivity in forming a self-aligned contact opening in the fabrication of integrated circuits.
(2) Description of the Prior Art
The self-aligned contact (SAC) technology has been widely adopted to reduce device area in the fabrication of integrated circuit devices. Referring to FIG. 1, there is illustrated a cross-sectional view of a partially completed integrated circuit device of the prior art. On a semiconductor substrate 10, gate electrode stacks 13 have been formed having a top layer 22 of silicon nitride. Silicon nitride spacers 24 are formed on the sidewalls of the gate electrode stacks. A thick layer of silicon oxide 28 covers the gate electrode stacks. The thickness A of the silicon oxide layer 28 over the gate electrodes stacks is greater than about 4000 Angstroms. It is desirable to have a thinner silicon oxide insulating layer 28 so that the metal contact to be formed will have a lower aspect ratio. A contact opening with a high aspect ratio is difficult to fill completely without voids.
However, a thinner silicon oxide insulating layer of 2500 Angstroms or less produces corner selectivity problems. When the contact opening 31 is etched through the silicon oxide layer 28, a polymer 32 forms on the sidewalls of the silicon oxide layer. This polymer will passivate the silicon nitride corner area 34 and prevent shorting of the metal to be formed within the opening 31 to the gate 13.
If the silicon oxide thickness A above the gate electrode stack is less than about 2500 Angstroms, some of the silicon nitride layers 22 and 24 will be etched away at the corner areas 34, as shown by the dashed line. This will cause the metal contact layer to short to the gate at the corner areas.
To prevent the undesirable etching of the silicon nitride layer 22 at the corners 34, the wafer temperature can be raised to between about 140 to 150.degree. C. This higher temperature prevents etching of the silicon nitride layer at the corners by reducing the etching effect of fluorine ions on the silicon nitride. However, a wafer temperature that high can burn the photoresist material. The photoresist material 30 can tolerate a temperature only as high as 110 to 120.degree. C. This temperature is not high enough to reduce the etching effect of fluorine ions.
U.S. Pat. No. 5,376,227 to Lee shows a multilayer resist process. U.S. Pat. No. 5,425,848 to Haisma et al shows a method of patterning an ultra-violet (UV) cured photoresist. U.S. Pat. No. 5,525,192 to Lee et al uses a resist film that is sensitive to UV rays.